Dual port memory circuit devices are well known in the art. Typically, the dual port memory is a random access memory having two address and data ports wherein two requests to the memory can be handled at the same time. Such a dual port memory or DPRAM is often made from an array of arrays of static RAM's or SRAM with attending logic control circuits. The DPRAM facilitates communication between parts of the system that are either incompatible in some way or that need to be kept busy on separate buses.
While DPRAM's can handle simultaneous address requests submitted on both of its address ports, the importance of data integrity requires the DPRAM not process write requests to identical addresses in the same memory cycle.
In one form of DPRAM of the prior art, the avoidance of identical address requests in the same memory cycle on the two address ports is left up to the user. Typically, this is accomplished by software programming. This leaves a problem of identical address requests potentially unresolved if the user forgets or incorrectly programs the system.
In an effort to obviate the need for the user to remedy this condition, hardware circuits have been developed and incorporated into the DPRAM chip to arbitrate and resolve identical address requests in the same memory cycle or the two ports. Typically, an arbitration circuit is in the form of a flip flop or cross-coupled NAND gates.
Another prior art hardware technique to resolve identical address requests in the same memory cycle to the two ports is to set up a selected-unselected relationship between the two ports. Thus, identical address requests in the same memory cycle to the two ports would result in the port designated the selected having preference over the port that is designated as the unselected. A variation of the selected-unselected technique is the fabrication of imbalanced transistors in the arbitration circuit such that one side would switch faster than the other, thereby resolving identical requests in the same memory cycle.
Although arbitration circuits of the prior art are able to resolve identical address requests in the same memory cycle to the two ports under nearly all circumstances, it is possible under certain circumstances that the arbitration circuits would be unable to resolve identical address requests. In particular, if the two address requests are simultaneously supplied to the arbitration circuit, the arbitration circuit will enter into a meta-state wherein it is unable to resolve the identical address request in the time when a selected-unselected result is needed.
Similarly, in the case of a selected-unselected circuit, if an address request to the selected port precedes the identical address request to the unselected port wherein the time delay between the two requests equals the time delay in the selected-unselected relationship, then the selected-unselected circuit would be unable to resolve the two identical address requests. In this situation, similar to the arbitration circuit, the selected-unselected circuit enters into a meta-state.